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MCM63P733A 1 motorola fast sram advance information 128k x 32 bit pipelined burstram synchronous fast static ram the MCM63P733A is a 4mbit synchronous fast static ram designed to pro- vide a burstable, high performance, secondary cache for the powerpc ? and other high performance microprocessors. it is organized as 128k words of 32 bits each, fabricated with high performance silicon gate cmos technology. this device integrates input registers, an output register, a 2bit address counter, and high speed sram onto a single monolithic circuit for reduced parts count in cache data ram applications. synchronous design allows pre- cise cycle control with the use of an external clock (k). cmos circuitry reduces the overall power consumption of the integrated functions for greater reliability. addresses (sa), data inputs (dqx), and all control signals except output enable (g ) and linear burst order (lbo ) are clock (k) controlled through positiveedgetriggered noninverting registers. bursts can be initiated with either adsp or adsc input pins. subsequent burst addresses can be generated internally by the MCM63P733A (burst sequence operates in linear or interleaved mode dependent upon state of lbo ) and con- trolled by the burst address advance (adv ) input pin. write cycles are internally selftimed and are initiated by the rising edge of the clock (k) input. this feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals. synchronous byte write (sbx ), synchronous global write (sgw ), and synchro- nous write enable (sw ) are provided to allow writes to either individual bytes or to all bytes. the four bytes are designated as aao, abo, aco, and ado. sba controls dqa, sbb controls dqb, etc. individual bytes are written if the selected byte writes sbx are asserted with sw . all bytes are written if either sgw is asserted or if all sbx and sw are asserted. for read cycles, pipelined srams output data is temporarily stored by an edgetriggered output register and then released to the output buffers at the next rising edge of clock (k). the MCM63P733A operates from a 3.3 v core power supply and all outputs operate on a 2.5 v or 3.3 v power supply. all inputs and outputs are jedec standard jesd85 compatible. ? MCM63P733A133 = 4 ns access/7.5 ns cycle (133 mhz) MCM63P733A117 = 4.2 ns access/8.5 ns cycle (117 mhz) MCM63P733A100 = 4.5 ns access/10 ns cycle (100 mhz) MCM63P733A90 = 5 ns access/11 ns cycle (90 mhz) ? 3.3 v + 10% / 5% core, power supply, 2.5 v or 3.3 v i/o supply ? adsp , adsc , and adv burst control pins ? selectable burst sequencing order (linear/interleaved) ? internally selftimed write cycle ? byte write and global write control ? singlecycle deselect ? sleep mode (zz) ? 100pin tqfp package powerpc is a trademark of ibm corp. this document contains information on a new product. specifications and information herein are subject to change without notice. order this document by MCM63P733A/d semiconductor technical data MCM63P733A tq package tqfp case 983a01 rev 1 3/24/98 ? motorola, inc. 1998
MCM63P733A 2 motorola fast sram write register a write register b enable register burst counter adsp g clr write register c write register d sba sbb sbc sbd se3 15 17 sgw dataout register enable register k2 k address register 17 datain register 128k x 32 array se2 lbo adv k adsc sa sa1 sa0 sw se1 k 4 32 2 2 k2 dqa dqd 32 functional block diagram
MCM63P733A 3 motorola fast sram pin assignment 71 72 dqc v ddq nc 69 70 66 67 68 64 65 61 62 63 3738 34 35 36 42 43 39 40 41 4546 44 60 59 58 57 56 55 54 53 52 51 31 32 33 74 75 76 77 78 79 80 50 49 48 47 dqb dqb v ss dqb dqb dqb dqb v ss v ddq dqb dqb v ddq v ss v ss v ddq dqc dqc dqc dqc dqc dqc dqc nc sa sa se1 sbd k sbc adv g sa0 sa sa sa sa nc nc nc lbo sa1 v dd v dd zz dqa v ss dqa dqa dqa dqa v ss v ddq dqa dqa v ss v ddq nc dqa dqd v dd v ss v ss v ddq dqd dqd dqd dqd dqd 73 nc 94 93 97 9695 89 88 92 91 90 86 85 87 100 99 98 81 82 83 84 10 9 12 11 15 14 13 17 16 20 19 18 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 8 sa sa sw se2 se3 v ss v dd nc nc v ddq v ss dqd dqd nc sa sa sa sa sa sa sa nc v ss adsp adsc sgw sba sbb
MCM63P733A 4 motorola fast sram pin descriptions pin locations symbol type description 85 adsc input synchronous address status controller: active low, interrupts any ongoing burst and latches a new external address. used to initiate a read, write, or chip deselect. 84 adsp input synchronous address status processor: active low, interrupts any ongoing burst and latches a new external address. used to initiate a new read, write, or chip deselect (exception e chip deselect does not occur when adsp is asserted and se1 is high). 83 adv input synchronous address advance: increments address count in accordance with counter type selected (linear/interleaved). (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b, c, d). 86 g input asynchronous output enable input. 89 k input clock: this signal registers the address, data in, and all control signals except g , lbo , and zz. 31 lbo input linear burst order input: this pin may be left floating; it will default as interleaved. low e linear burst counter (68k/powerpc). high e interleaved burst counter (486/i960/pentium). 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 36, 37 sa1, sa0 input synchronous address inputs: these pins must be wired to the two lsbs of the address bus for proper burst operation. these inputs are registered and must meet setup and hold times. 93, 94, 95, 96 (a) (b) (c) (d) sbx input synchronous byte write inputs: axo refers to the byte being written (byte a, b, c, d). sgw overrides sbx . 98 se1 input synchronous chip enable: active low to enable chip. negated high e blocks adsp or deselects chip when adsc is asserted. 97 se2 input synchronous chip enable: active high for depth expansion. 92 se3 input synchronous chip enable: active low for depth expansion. 88 sgw input synchronous global write: this signal writes all bytes regardless of the status of the sbx and sw signals. if only byte write signals sbx are being used, tie this pin high. 87 sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. if only byte write signals sbx are being used, tie this pin low. 64 zz input sleep mode: this active high asynchronous signal places the ram into the lowest power mode. the zz pin disables the rams internal clock when placed in this mode. when zz is negated, the ram remains in low power mode until it is commanded to read or write. data integrity is maintained upon returning to normal operation. 15, 41, 65, 91 v dd supply core power supply. 4, 11, 20, 27, 54, 61, 70, 77 v ddq supply i/o power supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss supply ground. 14, 16, 38, 39, 42, 43, 66 nc e no connection: there is no connection to the chip.
MCM63P733A 5 motorola fast sram truth table (see notes 1 through 5) next cycle address used se1 se2 se3 adsp adsc adv g 3 dqx write 2, 4 deselect none 1 x x x 0 x x highz x deselect none 0 x 1 0 x x x highz x deselect none 0 0 x 0 x x x highz x deselect none x x 1 1 0 x x highz x deselect none x 0 x 1 0 x x highz x begin read external 0 1 0 0 x x x highz x begin read external 0 1 0 1 0 x x highz read continue read next x x x 1 1 0 1 highz read continue read next x x x 1 1 0 0 dq read continue read next 1 x x x 1 0 1 highz read continue read next 1 x x x 1 0 0 dq read suspend read current x x x 1 1 1 1 highz read suspend read current x x x 1 1 1 0 dq read suspend read current 1 x x x 1 1 1 highz read suspend read current 1 x x x 1 1 0 dq read begin write external 0 1 0 1 0 x x highz write continue write next x x x 1 1 0 x highz write continue write next 1 x x x 1 0 x highz write suspend write current x x x 1 1 1 x highz write suspend write current 1 x x x 1 1 x highz write notes: 1. x = don't care. 1 = logic high. 0 = logic low. 2. write is defined as either 1) any sbx and sw low, or 2) sgw is low. 3. g is an asynchronous signal and is not sampled by the clock k. g drives the bus immediately (t glqx ) following g going low. 4. on write cycles that follow read cycles, g must be negated prior to the start of the write cycle to ensure proper write data setup times. g must also remain negated at the completion of the write cycle to ensure proper write data hold times. asynchronous truth table operation zz g i/o status read l l data out (dqx) read l h highz write l x highz deselected l x highz selected h x highz linear burst address table (lbo = v ss ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x10 x . . . x11 x . . . x00 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x00 x . . . x01 x . . . x10
MCM63P733A 6 motorola fast sram interleaved burst address table (lbo = v dd ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x00 x . . . x11 x . . . x10 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x10 x . . . x01 x . . . x00 write truth table cycle type sgw sw sba sbb sbc sbd read h h x x x x read h l h h h h write byte a h l l h h h write byte b h l h l h h write byte c h l h h l h write byte d h l h h h l write all bytes h l l l l l write all bytes l x x x x x absolute maximum ratings (see note 1) rating symbol value unit notes power supply voltage v dd 0.5 to + 4.6 v i/o supply voltage v ddq v ss 0.5 to v dd v 2 input voltage relative to v ss for any pin except v dd v in , v out 0.5 to v dd + 0.5 v 2 input voltage (threestate i/o) v it 0.5 to v ddq + 0.5 v 2 output current (per i/o) i out 20 ma package power dissipation p d 1.2 w 3 temperature under bias t bias 10 to + 85 c storage temperature t stg 55 to + 125 c notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. this is a steadystate dc parameter that is in effect after the power supply has achieved its nominal operating level. power sequencing is not necessary. 3. power dissipation capability is dependent upon package characteristics and use environment. see package thermal characteristics. package thermal characteristics rating symbol max unit notes junction to ambient (@ 200 lfm) singlelayer board fourlayer board r q ja 40 25 c/w 1, 2 junction to board (bottom) r q jb 17 c/w 3 junction to case (top) r q jc 9 c/w 4 notes: 1. junction temperature is a function of onchip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. per semi g3887. 3. indicates the average thermal resistance between the die and the printed circuit board. 4. indicates the average thermal resistance between the die and the case top surface via the cold plate method (mil spec883 method 1012.1). this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit.
MCM63P733A 7 motorola fast sram dc operating conditions and characteristics (v dd = 3.3 v + 10%, 5%, t a = 0 to 70 c, unless otherwise noted) recommended operating conditions: 2.5 v i/o supply (voltages referenced to v ss = 0 v) parameter symbol min typ max unit supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 2.375 2.5 2.9 v input low voltage v il 0.3 e 0.7 v input high voltage v ih 1.7 e v dd + 0.3 v input high voltage (i/o pins) v ih2 1.7 e v ddq + 0.3 v output low voltage (i ol = 2 ma) v ol e e 0.7 v output high voltage (i oh = 2 ma) v oh 1.7 e e v recommended operating conditions: 3.3 v i/o supply (voltages referenced to v ss = 0 v) parameter symbol min typ max unit supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 3.135 3.3 v dd v input low voltage v il 0.5 e 0.8 v input high voltage v ih 2 e v dd + 0.5 v input high voltage (i/o pins) v ih2 2 e v ddq + 0.5 v output low voltage (i ol = 8 ma) v ol e e 0.4 v output high voltage (i oh = 4 ma) v oh 2.4 e e v v ih 20% t khkh (min) v ss v ss 1.0 v figure 1. undershoot voltage
MCM63P733A 8 motorola fast sram supply currents parameter symbol min typ max unit notes input leakage current (0 v v in v dd ) i lkg(i) e e 1 m a 1, 2 output leakage current (0 v v in v ddq ) i lkg(o) e e 1 m a ac supply current (device selected, MCM63P733A133 all outputs open, freq = max) MCM63P733A117 includes v dd only MCM63P733A100 MCM63P733A90 i dda e e tbd ma 3, 4, 5 cmos standby supply current (device deselected, freq = 0, v dd = max, all inputs static at cmos levels) i sb2 e e tbd ma 6, 8 sleep mode supply current (sleep mode, freq = max, v dd = max, all other inputs static at cmos levels, zz v dd 0.2 v) i zz e e 2 ma 2, 7, 8 ttl standby supply current (device deselected, freq = 0, v dd = max, all inputs static at ttl levels) i sb3 e e tbd ma 6, 9 clock running (device deselected, MCM63P733A133 freq = max, v dd = max, all inputs MCM63P733A117 toggling at cmos levels) MCM63P733A100 MCM63P733A90 i sb4 e e tbd ma 3, 4, 5, 6, 8 static clock running (device deselected, MCM63P733A133 freq = max, v dd = max, all inputs MCM63P733A117 static at ttl levels) MCM63P733A100 MCM63P733A90 i sb5 e e tbd ma 6, 9 notes: 1. lbo pin has an internal pullup and will exhibit leakage currents of 5 m a. 2. zz pin has an internal pulldown and will exhibit leakage currents of 5 m a. 3. reference ac operating conditions and characteristics for input and timing. 4. all addresses transition simultaneously low (lsb) then high (msb). 5. data states are all zero. 6. device is deselected as defined by the truth table. 7. device in sleep mode as defined by the asynchronous truth table. 8. cmos levels for i/o's are v it v ss + 0.2 v or v ddq 0.2 v. cmos levels for other inputs are v in v ss + 0.2 v or v dd 0.2 v. 9. ttl levels for i/o's are v it v il or v ih2 . ttl levels for other inputs are v in v il or v ih . capacitance (f = 1.0 mhz, dv = 3.0 v, t a = 0 to 70 c, periodically sampled rather than 100% tested) parameter symbol min typ max unit input capacitance c in e 4 5 pf input/output capacitance c i/o e 7 8 pf
MCM63P733A 9 motorola fast sram ac operating conditions and characteristics (v dd = 3.3 v + 10%, 5%, t a = 0 to 70 c, unless otherwise noted) input timing measurement reference level 1.25 v . . . . . . . . . . . . . . input pulse levels 0 to 2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1.0 v/ns (20 to 80%) . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.25 v . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 2 unless otherwise noted . . . . . . . . . . . . . . read/write cycle timing (see notes 1 through 4) p sbl 63p733a133 133 mhz 63p733a117 117 mhz 63p733a100 100 mhz 63p733a90 90 mhz ui n parameter symbol min max min max min max min max unit notes cycle time t khkh 7.5 e 8.5 e 10 e 11 e ns clock high pulse width t khkl 3 e 3.4 e 4 e 4.4 e ns clock low pulse width t klkh 3 e 3.4 e 4 e 4.4 e ns clock access time t khqv e 4 e 4.2 e 4.5 e 5 ns output enable to output valid t glqv e 3.8 e 3.8 e 4.5 e 5 ns clock high to output active t khqx1 0 e 0 e 0 e 0 e ns 5, 6 clock high to output change t khqx2 1.5 e 1.5 e 1.5 e 1.5 e ns 6 output enable to output active t glqx 0 e 0 e 0 e 0 e ns 5, 6 output disable to q highz t ghqz e 3.8 e 3.8 e 4.5 e 5 ns 5, 6 clock high to q highz t khqz 1.5 7.5 1.5 8.5 1.5 10 1.5 11 ns 5, 6 setup times: address adsp , adsc , adv data in write chip enable t adkh t adskh t dvkh t wvkh t evkh 2 e 2 e 2 e 2 e ns hold times: address adsp , adsc , adv data in write chip enable t khax t khadsx t khdx t khwx t khex 0.5 e 0.5 e 0.5 e 0.5 e ns sleep mode standby t zzs e 2 x t khkh e 2 x t khkh e 2 x t khkh e 2 x t khkh ns sleep mode recovery t zzrec 2 x t khkh e 2 x t khkh e 2 x t khkh e 2 x t khkh e ns sleep mode high to q highz t zzqz e 15 e 15 e 15 e 15 ns notes: 1. write is defined as either any sbx and sw low or sgw is low. chip enable is defined as se1 low, se2 high, and se3 low whenever adsp or adsc is asserted. 2. all read and write cycle timings are referenced from k or g . 3. g is a don't care after write cycle begins. to prevent bus contention, g should be negated prior to start of write cycle. 4. in order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, fsram ac parametric specifications are always specified at v ddq /2. in some design exercises, it is desirable to evaluate timing using other reference levels. since the maximum test input edge rate is known and is given in the ac test conditions section of the data sheet as 1 v/ns, one can easily interpolate timing values to other reference levels. 5. this parameter is sampled and not 100% tested. 6. measured at 200 mv from steady state.
MCM63P733A 10 motorola fast sram output z 0 = 50 w r l = 50 w 1.25 v figure 2. ac test load figure 3. lumped capacitive load and typical derating curve 2000 1600 1200 800 400 0 lumped capacitance, c l (pf) 100 80 60 40 20 0 c l clock access time delay (ps) output 2400 200 600 1800 1400 1000 2200
MCM63P733A 11 motorola fast sram (c) pulldown voltage (v) pulldown i (ma) min i (ma) max 0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4 0 0 10 20 31 40 40 40 40 0 0 20 40 63 80 80 80 80 figure 4. typical output buffer characteristics v dd 1.6 1.25 0.3 0 040 80 current (ma) voltage (v) (b) pullup: v ddq = 3.3 v voltage (v) pullup i (ma) min i (ma) max 0.5 0 1.4 1.65 2.0 3.135 3.6 40 40 40 37 28 0 0 120 120 120 108 81 20 0 3.135 2.8 1.65 1.4 0 0 40 current (ma) voltage (v) 3.6 120 80 (a) pullup for v ddq = 2.5 v voltage (v) pullup i (ma) min i (ma) max 0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 38 38 38 30 27 0 0 0 105 105 105 83 75 40 15 0 2.9 2.5 2.3 1.25 0.8 0 0 40 105 current (ma) voltage (v)
MCM63P733A 12 motorola fast sram burst read single read adsc t khkl t khkh dqx e k adsp adv q(a) q(n) burst write adsp, sa sa ab t klkh cd se1 w q(b) q(b+1) t khqv burst wraps around q(b+2) q(b+3) q(b) d(c) d(c+1) d(c+2) d(c+3) q(d) t khqv deselected single read se2, se3 ignored g t khqz t khqx1 t khqx2 t ghqz t glqx w low = sgw low and / or sw and sbx low. note: e low = se2 high and se3 low. read/write cycles
zz e k ads adv sleep mode timing w g t zzqz ads high = both adsc, adsp high. note: ads low = adsc low or adsp low. idd t zzs t zzrec e low = se1 low, se2 high, se3 low. addr dq normal operation no reads or writes allowed in sleep mode no new reads or writes allowed normal operation i zz i (max) specifications will not be met if inputs toggle. zz MCM63P733A 13 motorola fast sram
MCM63P733A 14 motorola fast sram application information sleep mode a sleep mode feature, the zz pin, has been implemented on the MCM63P733A. it allows the system designer to place the ram in the lowest possible power condition by asserting zz. the sleep mode timing diagram shows the different modes of operation: normal operation, no read/write allowed, and sleep mode. each mode has its own set of constraints and conditions that are allowed. normal operation: all inputs must meet setup and hold times prior to sleep and t zzrec nanoseconds after re- covering from sleep. clock (k) must also meet cycle, high, and low times during these periods. two cycles prior to sleep, initiation of either a read or write operation is not allowed. no read/write: during the period of time just prior to sleep and during recovery from sleep, the assertion of either adsc , adsp , or any write signal is not allowed. if a write operation occurs during these periods, the memory array may be corrupted. validity of data out from the ram can not be guaranteed immediately after zz is asserted (prior to being in sleep). sleep mode: the ram automatically deselects itself. the ram disconnects its internal clock buffer. the external clock may continue to run without impacting the rams sleep cur- rent (i zz ). all inputs are allowed to toggle e the ram will not be selected and perform any reads or writes. however, if inputs toggle, the i zz (max) specification will not be met. nonburst synchronous operation although this burstram has been designed for powerpc e and other high end mpubased systems, these srams can be used in other high speed l2 cache or memory applications that do not require the burst address feature. most l2 caches designed with a synchronous interface can make use of the MCM63P733A. the burst counter feature of the burstram can be disabled, and the sram can be con- figured to act upon a continuous stream of addresses. see figure 4. control pin tie values example (h v ih , l v il ) nonburst adsp adsc adv se1 se2 lbo sync nonburst, pipelined sram h l h l h x note: alt hough x is specified in the table as a don't care, the pin must be tied either high or low. writes reads dq k q(b) q(a) addr a b cd ef gh w q(d) q(c) d(f) d(e) d(h) d(g) g figure 5. example configuration as nonburst synchronous sram se3 mcm 63p733a xx x x motorola memory prefix part number full part numbers e MCM63P733Atq133 MCM63P733Atq117 MCM63P733Atq100 MCM63P733Atq90 MCM63P733Atq133r MCM63P733Atq117r MCM63P733Atq100r MCM63P733Atq90r package (tq = tqfp) blank = trays, r = tape and reel speed (133 = 133 mhz, 117 = 117 mhz, 100 = 100 mhz, 90 = 90 mhz) ordering information (order by full part number)
MCM63P733A 15 motorola fast sram package dimensions tq package 100pin tqfp case 983a01 dim min max min max inches millimeters a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 b1 0.22 0.33 0.009 0.013 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 d 22.00 bsc 0.866 bsc e 16.00 bsc 0.630 bsc e1 14.00 bsc 0.551 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 l1 1.00 ref 0.039 ref l2 0.50 ref s 0.20 0.008 r1 0.08 0.003 r2 0.08 0.20 0.003 0.008 0 7 0 7 0 0 11 13 11 13 11 13 11 13 1 2 3 d1 20.00 bsc 0.787 bsc 0.020 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions d and e to be determined at seating plane c. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions d1 and b1 do include mold mismatch and are determined at datum plane h. 7. dimension b does not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.45 (0.018). ab 0.20 (0.008) h e d ab 0.20 (0.008) c d ab 0.20 (0.008) c d 0.10 (0.004) c 0.25 (0.010) s 0.05 (0.002) s ab m 0.13 (0.005) d s c e/2 d/2 e e1 d1 d d1/2 e1/2 e/2 4x 2x 30 tips 2x 20 tips d b a c h 1 3 2 100 81 80 51 50 31 30 1 plating section bb c1 c b b1 ???? ???? base metal a seating plane view ab s view ab a2 a1 r1 l2 l l1 r2 gage plane x view y b b x=a, b, or d
MCM63P733A 16 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 141, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 nishi-gotanda, shagawa-ku, tokyo, japan. 03-5487-8488 mfax ? : rmfax0@email.sps.mot.com t ouchtone 1-602-244-6609 asia / pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & c anada only 1-800-774-1848 51 ting kok road, tai po, n.t., hong kong. 852-26629298 http ://sps.motorola.com /mfax / home page : http ://motorola.com/sps / customer focus center: 1-800-521-6274 MCM63P733A/d ?

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